The Serial Peripheral Interface

Here's a little background information on the widely popular serial peripheral interface.

Here's the lowdown on SPI

The Serial Peripheral Interface (SPI) communication standard was devised by Motorola in the 1970’s, but is still widely used in even the most modern devices by many manufactures—typically for low-speed configuration of a chip. The SPI communication standard is capable of sufficient speed for the majority of applications (on the order of 10 MHz) and provides a simple 3-wire interface for sending data to a device.

In this tutorial we’ll walk you through the basics of communicating with an SPI device by 1) identifying and defining the signals used in the interface, 2) demonstrating an example use of the interface on a real-world device and 3) discussing some common implementation variations.

Interface Definition for SPI

Curious what MOSI stands for? Want to know exactly how the SPI signals work? Read below for all the gory details on the SPI.

The simple configuration

We’ll start of by addressing the simplest and most common configuration, which is the master-slave mode, shown below. In this configuration the controlling device (referred to as the “master” device) drives the clock, data and device selection signals to the device receiving data (referred to as the “slave” device). The slave device can optionally send data back to the master device. The notional operation of the SPI signals is illustrated in timing diagram below

The signals

The SPI standard consists of four signals:

  1. SCLK (serial clock)
  2. MOSI (master out / slave in)
  3. SS_N (slave select (not))
  4. MISO (master in / slave out)

So what do all these signals do?

The SCLK signal is the clock used to latch the data bits into the chip as they arrive and is generated by the master device. All other signals are setup during the HIGH clock cycle, and then latched into the chip at the falling edge of SCLK. The MOSI is the single-bit serial information being sent to the slave chip. The SS_N signal is used to inform the chip that it is to listen to the data line. In master-slave mode, every slave device gets own SS_N line. When the line goes LOW, information on the MOSI line is accepted into the chip. When a complete data word is sent in, the SS_N is returned to high to indicate that the data that was just sent to the chip should be registered in the appropriate memory location within the chip. If the SS_N line remains high during data transmission, the data on the MOSI line is ignored. In this way, multiple chips can be programed using a common clock (SCLK) and data bus (MOSI). The MISO line is a serial data line used to send data back from a slave to the master device, and it follows similar rules as the MOSI line. Each device may require a different communication sequence to retrieve information from the SPI device.

Use Case

In order to demonstrate the specific signals seen on SPI communication lines, we’ll walk through a specific example showing how a single master device can program multiple slave devices.

Master with multiple slave devices example

The device connections are shown in the figure below. Notice that multiple slave devices can be connected to a single master. Each of the slave devices shares the SCLK, MOSI and MISO signals; each slave device has an independent SS_N signal. In this example, the SS_N_0 line controls the VCO and the SS_N_1 line controls the DDS.

In this example, a complex programmable logic device (CPLD) programs an Analog Devices ADF4360 voltage controlled oscillator (VCO) and an Analog Devices AD9910 Direct Digital Synthesizer (DDS). For the purpose of this example, we will assume the DDS has already been programmed and focus on programming only the VCO—ensuring that the DDS ignores programming data sent to the VCO.

The datasheet for the ADF4360 VCO instructs on page 5 that a 22-bit data word is to be sent most significant bit (MSB) first followed by two control bits. In this device, the data word is loaded into the instruction register within the device upon reception, and the control bits direct the SPI state machine to place the information in a particular memory location within the device. For this example we’ll program the “N Counter Latch” (seen on page 13 of the datasheet) with the data word 0x00640 (hex). Converting 0x00640 (hex) to a 22-bit binary number, we get 0000000000011001000000 (binary). The control bits for addressing the “N Counter Latch” are 10 (binary). The timing diagram for programming the “N Counter Latch” of the ADF4360 is shown below.

Notice that the SS_N_1 line (slave select signal for the DDS) is HIGH throughout the programming sequence while the SS_N_0 line (slave select signal for the VCO) is LOW for 24 bit periods. This is because holding the slave select signal HIGH to a device will cause the device to ignore data coming in on the MOSI pin. In this example we want to ensure that only the VCO is programed, so the VCO’s slave select line is LOW during programming, and the DDS slave select signal is held HIGH.

Warning! Read the datasheet

While the basic concepts of SPI are consistent between devices, some manufactures have chosen to implement the communication link with slight variations.

Your mileage may vary

Although this can be somewhat annoying, the changes are usually very minimal and do not increase implementation time. Some variations include (but are not limited to) which clock edge the data is latched on (rising / falling), polarity of the slave select signal (active low / active high), data word bit order (MSB / LSB), data word composition content and order (address / data / command), signal names, etc. Additionally, each device manufacture will have a minimum and maximum clock speed that the SPI link can be operated.

More Information

More information on the SPI communication protocol can be found in at the following locations: Wikipedia, EE Times, and