Digital Timing Diagrams

Your timing diagram journey begins here.

Timing diagram basics

Digital timing diagrams are a time domain representation of digital logic levels. Each row in a given diagram corresponds to a different signal. In the figure below you’ll see three signals: clk, data and dval. Each of the columns in the figure, labeled 1 – 10, represent a single period of signal clk. Following the columns from left to right shows the voltage variations of these signals over time. A digital timing diagram is essentially the equivalent of an oscilloscope or more accurately a logic analyzer display. These diagrams are frequently used as a tool to describe digital interfaces. Timing diagrams can be used to debug hardware, describe communication protocols and the list goes on.

Timing Diagram Details

Now that we've covered the basic structure, let's get into more of the nitty gritty.

Digging deeper

The signals included in a timing diagram vary depending on application and component specifics, however, in a synchronous system, at least one row will be dedicated to the system clock. A signal shown at a high level corresponds to a digital ‘1’ and a signal at a low level corresponds to ‘0’. Some signals may show a simultaneous high and low levels such as 'data' in the figure below. In this case, the high and low levels of the data row represent a multi-bit signal. The values listed within (A0, 4B, 04 and 18) are the values at that particular instance. In this case the values are given in hex and one can infer that data represents an 8-bit signal. Areas that are greyed out represent a “don’t care” and a ‘Z’ depicts high impedance.

This covers the basics, for a more exhaustive listing of the items that can be found on a timing diagram, refer to our digital timing diagram key. Don't forget to check out our other articles covering topics such as SPI and I2C.